Vitorian LLC and ADIUVO Engineering & Training Ltd UK have the pleasure to introduce this new course on SoC accelerating techniques intended for managing directors, technologists and project managers working within the financial industry.
Outline of Course
Designed for those in the financial market using Programmable Logic to implement High Frequency Trading applications. The course will demonstrate how System on Chip devices like the Zynq 7000 and Zynq MPSoC can be used combined with High Level Synthesis (HLS) to accelerate the system performance. High Level Synthesis enables the algorithm to be developed using high level languages like C / C++, these can be
The course will be targeted to the PicoZed Development board ($399 7030) which can be mounted upon the PicoZed FMC Carrier Card V2 ($349) which provides a SFP+ cage for one 10G Ethernet link. A second GTX lane is broken out the to the FMC connector on the FMC Carrier card, as such to gain access to a second 10G ethernet port a FMC mezzanine card can be used. The Gigabit ethernet within the PS is also provided on the FMC board.
The development tool for the system will examine both Vivado, Vivado HLS and SDSoC ($999 locked license, $1399 floating).
Alternative for teaching could be MicroZed which is more self- contained – TBD as to approach
- Why are we here what are the driving factors of the fintech industry
- Introduction to the Zynq and MPSoC – Architecture, Peripherals, PL, PS / PL Interconnect
- PS / PL Interconnects – General Purpose, High Purpose, ACP, ACE.
- Vivado Introduction – UltraFast design practices
- Vivado HLS Introduction – How does HLS work – optimisations pipelining, loop unrolling, iteration interval etc.
- Vivado HLS – Interfacing options, simulation and verification
- SDSoC – Introduction – System Optimising complier / Operating systems used
- SDSoC – Platform definition – what makes a HW platform / what makes a SW Platform
- SDSoC flow – Develop algorithm on cores, identify bottlenecks and then accelerate to PL
- SDSoC Libraries – Using the Vivado HLS libs – Math, Video, Linear Alg, Arbitrary Precision, IP Lib
- SDSoC Memory management – Using SDS Alloc in place of Malloc
- SDSoC optimisation
- Iteration Interval – what it means, how its reported how we define it
- Loop Unrolling – impact of nested loops
- Memory optimisation
- Interfacing – Data Motion Network
- Example 1 Walk through and demonstration
- Example 2 Walk through and demonstration
- Wrap Up and Questions not answered so far.
- SDSoC AES / SHA Example
- Ethernet offloading example 1 G Example